![]() ![]() In the circuit of fig.14-7, if the outputs are withdrawn from the complement terminal Q of the flip-flop, this circuit can be used as binary down counter. , 0, and goes back to 15 and decreases again. 4 bit down counter coefficient starts from the binary number of 15 and changes as 14, 13, 12. In the down counter, the binary coefficient decreases by 1 per clock pulse. Binary Down Counterīinary down counter is the binary counter that is counted in reverse(that is, the counter that decreases from 1111 to 1110, 1101). The ripple counter is sometimes called asynchronous counter. The signal is delivered in ripple form through the counter. The flip-flops of this counter are connected quickly one by one and change. This is becomes the output value of A4 changes from "0" to "1". If it is supposed that A4 is connected to the next register with the same formula, the transition of A4’s output value cannot operate the next register. Therefore, the value of A2 changes from "1" to "0" and this makes A3 as the complement, and A3 changes from "1" to "0" and makes A4 as the complement. The value of A1 changes from "1" to "0" and this operates the register of A2 so A2 takes the complement. The arrow in the table shows the emphasis of these transitions. ![]() For example, let’s investigate the transition from coefficient 0111 to 1000. Also, whenever the value of A2 changes from “1” to “0”, the value of A3 will become the complement. Whenever the value of A1 changes from “1” to “0”, the value of A2 will become the complement. The lowest bit A1 should become a complement per every clock pulse. To understand the operation of binary ripple counter, take a look at the counter sequence in fig.14-7. 14-7Count Sequence of Binary Ripple Counter ![]()
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |